Cypress Semiconductor /psoc63 /PERI /PPU_GR[10] /ATT0

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Interpret as ATT0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UR)UR 0 (UW)UW 0 (UX)UX 0 (PR)PR 0 (PW)PW 0 (PX)PX 0 (NS)NS 0 (PC_MASK_0)PC_MASK_0 0PC_MASK_15_TO_10REGION_SIZE 0 (PC_MATCH)PC_MATCH 0 (ENABLED)ENABLED

Description

PPU region attributes 0 (slave structure)

Fields

UR

See corresponding field for PPU structure with programmable address.

UW

See corresponding field for PPU structure with programmable address.

UX

See corresponding field for PPU structure with programmable address.

Note that this register is constant ‘1’; i.e. user execute accesses are ALWAYS allowed.

PR

See corresponding field for PPU structure with programmable address.

PW

See corresponding field for PPU structure with programmable address.

PX

See corresponding field for PPU structure with programmable address.

Note that this register is constant ‘1’; i.e. user execute accesses are ALWAYS allowed.

NS

See corresponding field for PPU structure with programmable address.

PC_MASK_0

See corresponding field for PPU structure with programmable address.

PC_MASK_15_TO_1

See corresponding field for PPU structure with programmable address.

REGION_SIZE

See corresponding field for PPU structure with programmable address.

Note: this field is read-only. Its value is chip specific.

PC_MATCH

See corresponding field for PPU structure with programmable address.

ENABLED

See corresponding field for PPU structure with programmable address.

Links

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